Built-in Fault-tolerant Computing Paradigm for Resilient Large-scale Chip Design: A Self-test, Self-diagnosis, and Self-repair-based Approach
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The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs.
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The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs.
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