We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking ...
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We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore's law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.
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Add this copy of Integrated System-Level Modeling of Network-on-Chip to cart. $168.69, new condition, Sold by Ingram Customer Returns Center rated 5.0 out of 5 stars, ships from NV, USA, published 2010 by Springer.
Add this copy of Integrated System-Level Modeling of Network-on-Chip to cart. $31.11, good condition, Sold by Anybook rated 4.0 out of 5 stars, ships from Lincoln, UNITED KINGDOM, published 2006 by Springer.
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This is an ex-library book and may have the usual library/used-book markings inside. This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item, 550grams, ISBN: 9781402048258.
Add this copy of Integrated System-Level Modeling of Network-on-Chip to cart. $100.07, good condition, Sold by Bonita rated 4.0 out of 5 stars, ships from Santa Clarita, CA, UNITED STATES, published 2006 by Springer-Verlag.
