Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.
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Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.
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Add this copy of On-Chip Training Npu - Algorithm, Architecture and Soc to cart. £132.24, new condition, Sold by GreatBookPricesUK5 rated 4.0 out of 5 stars, ships from Castle Donington, DERBYSHIRE, UNITED KINGDOM, published 2023 by Springer.
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New. Sewn binding. Cloth over boards. 237 p. Contains: Unspecified, Illustrations, black & white, Illustrations, color, Tables, color. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
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